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64mx72 bits registered ddr sdram dimm this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.1 / may 2004 1 hymd564g726b(l)f8n-d43/j revision history no. history draft date remark 0.1 defined target spec. may 2004 preliminary
64mx72 bits registered ddr sdram dimm this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.1 / may 2004 2 hymd564g726b(l)f8n-d43/j description preliminary hynix hymd564g726b(l)f8n-d43/j series is registered 184-pin double data rate synchronous dram dual in-line memory modules (dimms) which are organized as 64m x 72 high-speed memory arrays. hynix hymd564g726b(l)f8n-d 43/j series consists of nine 64m x 8 ddr sdram in fbga packages on a 184pin glass- epoxy substrate. hynix hymd564g726b(l)f8n-d43/j series pr ovide a high performance 8-byte interface in 5.25" width form factor of industry standard. it is suitable for easy interchange and addition. hynix hymd564g726b(l)f8n-d43/j series is designed for hi gh speed of up to 166/200mhz and offers fully synchro- nous operations referenced to both rising and falling edges of differential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inte rnally pipelined and 2-bit pref etched to achieve very high bandwidth. all input and output voltage levels are compat ible with sstl_2. high speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. hynix hymd564g726b(l)f8n-d43/j series incorporates spd(serial presence detect). serial presence detect function is implemented via a serial 2,048-bit eeprom. the first 128 bytes of serial pd data are programmed by hynix to identify dimm type, capacity and other the information of dimm and the last 128 bytes are available to the customer. features ordering information part no. power supply clock frequency interface form factor hymd564g726b(l)f8n-d43 v dd =2.6v v ddq =2.6v 200mhz (*ddr400) sstl_2 184pin registered dimm 5.25 x 1.125 x 0.15 inch hymd564g726b(l)f8n-j v dd =2.5v v ddq =2.5v 166mhz (*ddr333) ? 512mb (64m x 72) registered ddr dimm based on 64m x 8 ddr sdram ? jedec standard 184-pin du al in-line memory module (dimm) ? error check correction (ecc) capability ? registered inputs with one-clock delay ? phase-lock loop (pll) clock driver to reduce loading ? 2.6v +/- 0.1v vdd and vddq power supply for ddr400, 2.5v +/- 0.2v vdd and vddq for ddr333 supported ? all inputs and outputs ar e compatible with sstl_2 interface ? fully differential clock op erations (ck & /ck) with 166/200mhz ? programmable cas latency 3 for ddr400, 2.5 for ddr333 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? tras lock-out function supported ? internal four bank operations with single pulsed ras ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms * jedec defined specifications compliant
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 3 pin description pin assignment pin pin description pin pin description ck0, /ck0 differential clock inputs vddq dqs power supply cs0 chip select input vss ground cke0 clock enable input vref reference power supply /ras, /cas, /we commend sets in puts vddspd power supply for spd a0 ~ a12 address sa0~sa2 e 2 prom address inputs ba0, ba1 bank address scl e 2 prom clock dq0~dq63 data inputs/outputs sda e 2 prom data i/o cb0~cb7 data strobe inputs/o utputs wp write protect flag dqs0~dqs17 data strobe inputs/outputs vddid vdd identification flag dm0~7 data-in mask du do not use vdd power supply nc no connection /reset reset enable feten fet enable pin name pin name pin name pin name pin name pin name 1 vref 32 a5 62 vddq 93 vss 124 vss 154 /ras 2 dq0 33 dq24 63 /we 94 dq4 125 a6 155 dq45 3 vss 34 vss 64 dq41 95 dq5 126 dq28 156 vddq 4 dq1 35 dq25 65 /cas 96 vddq 127 dq29 157 /cs0 5 dqs0 36 dqs3 66 vss 97 dm0 128 vddq 158 /cs1* 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3 159 dm5 7 vdd 38 vdd 68 dq42 99 dq7 130 a3 160 vss 8 dq3 39 dq26 69 dq43 100 vss 131 dq30 161 dq46 9 nc 40 dq27 70 vdd 101 nc 132 vss 162 dq47 10 /reset 41 a2 71 nc 102 nc 133 dq31 163 nc 11 vss 42 vss 72 dq48 103 nc 134 cb4 164 vddq 12 dq8 43 a1 73 dq49 104 vddq 135 cb5 165 dq52 13 dq9 44 cb0 74 vss 105 dq12 136 vddq 166 dq53 14 dqs1 45 cb1 75 du 106 dq13 137 ck0 167 a13, feten* 15 vddq 46 vdd 76 du 107 dm1 138 /ck0 168 vdd 16 nc 47 dqs8 77 vddq 108 vdd 139 vss 169 dm6 17 nc 48 a0 78 dqs6 109 dq14 140 dm8 170 dq54 18 vss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 vss 80 dq51 111 cke1* 142 cb6 172 vddq 20 dq11 51 cb3 81 vss 112 vddq 143 vddq 173 nc 21 cke0 52 ba1 82 vddid 113 ba2* 144 cb7 174 dq60 22 vddq key 83 dq56 114 cb7 key 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 vss 176 vss 24 dq17 54 vddq 85 vdd 116 vss 146 dq36 177 dm7 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 vss 56 dqs4 87 dq58 118 a11 148 vdd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2 149 dm4 180 vddq 28 dq18 58 vss 89 vss 120 vdd 150 dq38 181 sa0 29 a7 59 ba0 90 nu 121 dq22 151 dq39 182 sa1 30 vddq 60 dq35 91 sda 122 a8 152 vss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd * these are not used on this module but may be used for other module in 184pin dimm family
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 4 functional block diagram note : 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ) : strap out (open) : v dd = v ddq strap in (v ss ) : v dd v ddq 5. sdram placement alternates between the back and front sides of the dimm. 6. address and control resistors should be 22 ohms. cko, /cko------pll* * wire per clock loading table/wiring diagram a0-a13 /ras /cas cke /we ra0-ra13-> : a0->a13 : sdrams d0-d8 /rras->/ras : sdrams d0-d8 /rcas->/cas : sdrams d0-d8 rckeo->cke : sdrams d0-d8 /rwe->we : sdrams d0-d8 /s ba0-ba1 /rs0->/cso : sdrams d0-d8 rba0-rba1-> : ba0->ba1 : sdrams d0-d8 r e g i s t e r /reset /pck pck dq00 dq01 dq02 dq03 dq04 dq05 dq06 dq07 dm /cs dqs d0 dm /cs dqs d1 dm /cs dqs d2 dm /cs dqs dm /cs dqs dm /cs dqs d5 dm /cs dqs dm /cs dqs d7 dm0 dqs0 dm4 dqs4 dm1 dqs1 dm2 dqs2 dm3 dqs3 dm7 dqs7 dm6 dqs6 dm5 dqs5 /rs0 d3 d6 d4 dm /cs dqs dm8 dqs8 d8 wp a0 a1 a2 sda sa0 sa1 sa2 serial pd scl vddspd vdd vref vss serial pd do-d8 do-d8 do-d8 strap:see note 4 vddq vddid do-d8 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq08 dq09 dq10 dq11 dq12 dq13 dq14 dq15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 5 absolute maximum ratings note : operation at above ab solute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vddq must not exceed the level of vdd. 2. vil (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. the value of vref is ap proximately equal to 0.5vddq. 4. for ddr400, vdd=2.6v +/- 0.1v, vddq=2.6v+/-0.1v parameter symbol rating unit operating temperature (ambient) ta 0 ~ 70 o c storage temperature tstg -55 ~ 125 o c voltage on any pin relative to vss vin, vout -0.5 ~ 3.6 v voltage on vdd relative to vss vdd -0.5 ~ 3.6 v voltage on vddq relative to vss vddq -0.5 ~ 3.6 v output short circuit current ios 50 ma power dissipation pd 1.0 x # of components w soldering temperature t time tsolder 260 / 10 o c / sec parameter symbol min typ. max unit note power supply voltage vdd 2.3 2.5 2.7 v power supply voltage vdd 2.5 2.6 2.7 v 4 power supply voltage vddq 2.3 2.5 2.7 v 1 power supply voltage vdd 2.5 2.6 2.7 v 1,4 input high voltage vih vref + 0.15 - vddq + 0.3 v input low voltage vil -0.3 - vref - 0.15 v 2 termination voltage vtt vref - 0.04 vref vref + 0.04 v reference voltage vref 0.49*vddq 0.5*vddq 0.51*vddq v 3
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 6 ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltage, dq, dq s and dm signals vih(ac) vref + 0.31 v input low (logic 0) voltage, dq, dq s and dm signals vil(ac) vref - 0.31 v input differential voltage, ck and /ck inputs vid(ac) 0.7 vddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 parameter value unit reference voltage vddq x 0.5 v termination voltage vddq x 0.5 v ac input high level voltage (vih, min) vref + 0.31 v ac input low level voltage (vil, max) vref - 0.31 v input timing measurement reference level voltage vref v output timing measurement reference level voltage vtt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (rt) 50 ? series resistor (rs) 25 ? output load capacitance for access time measurement (cl) 30 pf
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 7 capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.5v to 2.7v, vodc = vddq/2, vopeak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guarant eed by design and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input capacitance a0 ~ a12, ba0, ba1 cin1 7 12 pf input capacitance /ras, /cas, /we cin2 7 12 pf input capacitance cke0 cin3 7 12 pf input capacitance cs0 cin4 7 12 pf input capacitance ck0, /ck0 cin5 7 14 pf data input / output capacitance dq0 ~ dq63, dqs0 ~ dqs17 cio1 6 11 pf data input / output capacitance cb0 ~ cb7 cio2 6 11 pf v ref v tt r t =50 ? zo=50 ? c l =30pf output
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 8 dc characteristics i (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v in = 0 to 3.6v, all other pi ns are not tested under v in =0v 2. d out is disabled, v out =0 to 2.7v parameter symbol min. max unit note input leakage current add, cmd, /cs, /cke ili -2 2 ua 1 ck, /ck -4 4 output leakage current ilo -10 10 ua 2 output high voltage voh vtt + 0.76 - v ioh = -15.2ma output low voltage vol - vtt - 0.76 v iol = +15.2ma
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 9 dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) parameter symbol test condition speed unit note -d43 -j operating current idd0 one bank; active - precharge ; trc=trc(min); tck= tck(min) ; dq,dm and dqs inputs changing twice per clock cycle ; address and control inputs changing once per clock cycle 2000 1910 ma operating current idd1 one bank ; active - read - precharge ; burst length = 4 ; trc=trc(min); tck= tck(min) ; address and control inputs changing once per clock cycle 2450 2270 ma precharge power down standby current idd2p all banks idle ; power down mode ; cke= low, tck= tck(min) 740 ma idle standby current idd2f /cs = high, all banks idle ; tck= tck(min) ; cke = high ; address and control inputs changing once per clock cycle. vin = vref for dq, dqs and dm 965 ma active power down standby current idd3p one bank active ; power down mode ; cke= low, tck= tck(min) 758 ma active standby current idd3n /cs= high; cke = high; one bank; active-precharge; trc = tras(max); tck = t ck (max); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 1100 1055 ma operating current idd4r burst = 2 ; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck= tck (min); iout = 0ma 3170 2900 ma operating current idd4w burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck = tck (min); dq, dm, and dqs inputs changing twice per clock cycle 3170 2900 auto refresh current idd5 trc = trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 3050 2870 self refresh current idd6 cke =< 0.2v; external clock on; tck = tck(min) normal 395 ma low power 373 ma operating current - four bank operation idd7 four bank interleaving with bl=4 refer to the following page for detailed test condition 5510 4790 ma
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 10 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -d43 -j unit note min max min max row cycle time trc 55 - 60 - ns auto refresh row cycle time trfc 70 - 72 - ns row active time tras 40 70k 42 70k ns active to read with auto precharge delay trap trcd or trp(min) - trcd or trp(min) -ns16 row address to column address delay trcd 15 - 18 - ns row active to row active delay trrd 10 - 12 - ns column address to column address delay tccd 1 - 1 - ck row precharge time trp 15 - 18 - ns write recovery time twr 15 - 15 - ns write to read command delay twtr 2 - 1 - ck auto precharge write recovery + precharge time tdal (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) ck 15 system clock cycle time cl = 3 tck 510- - ns cl = 2.5 6 12 6 12 clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew tac -0.7 0.7 -0.7 0.7 ns dqs-out edge to clock edge skew tdqsck -0.55 0.55 -0.6 0.6 ns dqs-out edge to data-out edge skew tdqsq - 0.4 0.4 ns data-out hold time from dqs tqh thp -tqhs - thp -tqhs -ns1, 10 clock half period thp min (tcl,tch) - min (tcl,tch) -ns1,9 data hold skew factor tqhs - 0.5 - 0.55 ns 10 data-out high-impedance window from ck, /ck thz tac(max) -0.7 0.7 ns 17 data-out low-impedance window from ck, /ck tlz -0.7 0.7 -0.7 0.7 ns 17 input setup time (fast slew rate) tis 0.6 - 0.75 - ns 2,3,5,6 input hold time (fast slew rate) tih 0.6 - 0.75 - ns 2,3,5,6 input setup time (slow slew rate) tis 0.7 - 0.8 - ns 2,4,5,6 input hold time (slow slew rate) tih 0.7 - 0.8 - ns 2,4,5,6 input pulse width tipw 2.2 - 2.2 - ns 6 write dqs high level width tdqsh 0.35 - 0.35 - ck
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 11 ac characteristics (ac operating conditions unless otherwise noted) - continued - note : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the cloc k : a0~a12, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 5. ck, /ck slew rates are >=1.0v/ns, ie, >=2.0v/ns differential. 6. these parameters quarantee device timing, but they are not necessarily tested on each de vice, and they may be quaranteed by design or tester correlation. 7. data latched at both rising and fall ing edges of data strobes(ldqs/udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after se lf refresh exit command, where cke is held high, is required to co mplete self refresh exit and lo ck the internal dll circuit of ddr sdram. 9. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the dev ice (i.e. this value can be greater than the minimum specification limits for tcl and tch). parameter symbol -d43 -j unit note min max min max write dqs low level width tdqsl 0.35 - 0.35 - ck clock to first rising edge of dqs-in tdqss 0.72 1.28 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) tds 0.4 - 0.45 - ns 6,7,11~13 data-in hold time to dqs-in (dq & dm) tdh 0.4 - 0.45 - ns dq & dm input pulse width tdipw 1.75 - 1.75 - ns 6 read dqs preamble time trpre 0.9 1.1 0.9 1.1 ck read dqs postamble time trpst 0.4 0.6 0.4 0.6 ck write dqs preamble setup time twpres 0 - 0 - ck write dqs preamble hold time twpreh 0.25 - 0.25 - ck write dqs postamble time twpst 0.4 0.6 0.4 0.6 ck mode register set delay tmrd 2 - 2 - ck exit self refresh to any executable command txsc 200 - 200 - ck 8 average periodic refresh interval trefi - 7.8 - 7.8 us input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 12 10. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists o f tdqsqmax, the pulse width dist ortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p- channel to n-channel variation of the output drivers. 11 . this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 12. i/o setup/hold plateau derating. this derating table is us ed to increase tds/tdh in case where the input level is flat b elow vref +/-310mv for a duration of up to 2ns. 13. i/o setup/hold delta inverse slew rate derating. this derating table is used to increase tds/tdh in case where the dq a nd dqs slew rates differ. the de lta inverse slew rate is calculated as (1/s lewrate1)-(1/slewrate2). for example, if slew rate 1=0.5v/ns and slew rate2 = 0.4v /n then the delta inverse slew rate = -0.5ns/v. 14. dqs, dm and dq input slew rate is specified to prev ent double clocking of data and preserve setup and hold times. signal transi tions through the dc region must be monotonic. 15. tdal = (twr / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest i nteger. tck is equal to the actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2 ) + (3), tdal = 5 clock 16. for the parts which do not has internal ras lockout ci rcuit, active to read with auto precharge delay should be tras - bl/2 x tck. 17. thz and tlz transitions occur in the same access time windows as valid data trasitions. these parameters are not refer enced to a specific voltage level but specify when the de vice output is no longer driving (hz), or begins driving (lz). input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 000 +/-0.25 +50 +50 +/- 0.5 +100 +100
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 13 simplified command truth table note : 1. ldm/ udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 12 and ba 0 ~ba 1 used for mode registering duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+t rp ). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+t dpl +t rp ). last data-in to prechage delay(t dpl ) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a 10 /ap is high when row precharge command being issued, ba 0 /ba 1 are ignored and all banks are selected to be precharged. command cken-1 cken /cs /ras /cas /we add r a10/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect hx hxxx x1 no operation lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 14 package dimensions front 128.95 5.077 131.35 5.171 133.35 5.25 28.575 1.125 3.0 0.118 17.80 0.700 0.098 (2x)4.00 0.157 back : (single-sided) (2) 0 2.50 side 2.99 0.110max 4.00 0.157 1.27+/-0.10 0.05+/-0.004 note) all dimension are typical unless otherwise stated. millimeters inches register pll register
serial presence detect rev. 0.1 / may 2004 15 spd specification (64m x 72 registered ddr dimm)
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 16 serial presence detect byte# function description function supported hexa value note -d43 -j -d43 -j 0 number of bytes written into serial me mory at module manufacturer 128 bytes 80h 1 total number of bytes in spd device 256 bytes 08h 2 fundamental memory type ddr sdram 07h 3 number of row address on this assembly 13 0dh 1 4 number of column address on this assembly 11 0bh 1 5 number of physical banks on dimm 1bank 01h 6 module data width 72 bits 48h 7 module data width (continued) - 00h 8 module voltage interface levels(vddq) sstl 2.5v 04h 9 ddr sdram cycle time at cas latency=2.5(tck) 5.0ns 6.0ns 50h 60h 2 10 ddr sdram access time from clock at cl=2.5 (tac) +/-0.7ns 70h 2 11 module configuration type ecc 02h 12 refresh rate and type 7.8us & self refresh 82h 13 primary ddr sdram width x8 08h 14 error checking ddr sdram data width x8 08h 15 minimum clock delay for back -to-back random column address(tccd) 1 clk 01h 16 burst lengths supported 2,4,8 0eh 17 number of banks on each ddr sdram 4 banks 04h 18 cas latency supported 2, 2.5, 3 2, 2.5 1ch 0ch 19 cs latency 0 01h 20 we latency 1 02h 21 ddr sdram module attributes registered, pll 26h 22 ddr sdram device attributes : general +/-0.2voltage tolerance, concurrent auto precharge tras lock out c0h 23 ddr sdram cycle time at cl=2.0(tck) 6.0ns 7.5ns 60h 75h 2 24 ddr sdram access time from clock at cl=2.0(tac) +/-0.7ns 70h 2 25 ddr sdram cycle time at cl=1.5(tck), 2.0(tck) 7.5ns - 75h - 2 26 ddr sdram access time from clock at cl=1.5(tac) +/-0.75ns - 75h - 2 27 minimum row precharge time(trp) 15ns 18ns 3ch 48h 28 minimum row activate to row active delay(trrd) 10ns 12ns 28h 30h 29 minimum ras to cas delay(trcd) 15ns 18ns 3ch 48h 30 minimum active to precharge time(tras) 40ns 42ns 28h 2ah 31 module row density 512mb 80h 32 command and address signal input setup time(tis) 0.60ns 0.75ns 60h 75h 33 command and address signal input hold time(tih) 0.60ns 0.75ns 60h 75h 34 data signal input setup time(tds) 0.40ns 0.45ns 40h 45h 35 data signal input hold time(tdh) 0.40ns 0.45ns 40h 45h 36~40 reserved for vcsdram undefined 00h 41 minimum active / auto-refresh time ( trc) 55ns 60ns 37h 3ch 42 minimum auto-refresh to active/auto-refresh command period(trfc) 70ns 72ns 46h 48h 43 maximum cycle time (tck max) 10ns 12ns 28h 30h 44 maximim dqs-dq skew time(tdqsq) 0.4ns 28h 45 maximum read data hold skew factor(tqhs) 0.5ns 50h 46~61 superset information(may be used in future) undefined 00h 62 spd revision code initial release 00h 63 checksum for bytes 0~62 - bfh 4fh
hymd564g726b(l)f8n-d43/j rev. 0.1 / may 2004 17 serial presence detect - continued - note : 1. the bank address is excluded 2. this value is based on the component specification 3. these bytes are programmed by code of date week & date year 4. these bytes apply to hynix?s own module serial number system 5. these bytes undefined and coded as ?00h? 6. refer to hynix web site byte 85~86, low power part byte# function description function supported hexa value note d43 j d43 j 64 manufacturer jedec id code hynix jedec id adh 65~71 --------- manufacturer jedec id code - 00h 72 manufacturing location hynix(korea area) hsa(united states area) hse(europe area) hsj(japan area) singapore asia area 0*h 1*h 2*h 3*h 4*h 5*h 6 73 manufacture part number(hynix memory module) h 48h 74 -------- manufacture part number(hynix memory module) y 59h 75 -------- manufacture part number(hynix memory module) m 4dh 76 manufacture part number (ddr sdram) d 44h 77 manufacture part number(memory density) 5 35h 78 manufacture part number(module depth) 6 36h 79 ------- manufacture part number(module depth) 4 34h 80 manufacture part number(module type) g 47h 81 manufacture part number(data width) 7 37h 82 -------manufacture part number(data width) 2 32h 83 manufacture part number(refresh, # of bank.) 6(8k refresh,4bank) 36h 84 manufacture part number(component generation) b 42h 85 manufacture part number(component package type) f 46h 86 manufacture part number(component configuration) 8 38h 87 manufacture part number(module revision) n 4eh 88 manufacture part number(minimum cycle time) d j 44h 4ah 89 manufacture part number(minimum cycle time) 4 - 34h - 90 manufacture part number(minimum cycle time) 3 - 33h - 91 manufacture revision code(for component) - - - - 92 manufacture revision code (for pcb) - - - - 93 manufacturing date(year) - - - - 3 94 manufacturing date(week) - - - - 3 95~98 module serial number - - - - 4 99~127 manufacturer specific data (may be used in future) undefined 00h 5 128~255 open for customer use undefined 00h 5 byte # function description function supported hexa value note 85 manufacture part number(low power part) l 4ch 86 manufacture part number(component configuration) f 46h

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